1. Technical Field
The present invention relates to a simulation method and a simulation apparatus for a semiconductor integrated circuit, and more particularly, to a circuit simulation method and apparatus that carry out a highly accurate circuit simulation while taking into consideration effects that stress has on the electrical characteristics of a transistor.
2. Related Art
With the enhanced performance and integration of large scale integrated (LSI) circuits, it is increasingly important to minimize the isolation regions that electrically isolate the elements on semiconductor substrates. Semiconductor processing techniques involving sub-0.18 Mm for the minimum line width usually employ shallow trench isolation (STI) technology, which includes forming trenches between the elements and depositing insulating films in the formed trenches, thus realizing isolation of the elements.
When STI technology is used, the active region, where semiconductor elements are formed, and the STI region, which is made of an insulating film, have different heat expansion coefficients, resulting in stress (STI stress) applied to the interface between the active region and the STI region during the heat treatment step. The active region has a larger heat expansion coefficient than that of the STI region, and thus, for example, turns into a relaxed state in raised temperature. In lowered temperature, compressive stress is applied to the active region due to its shrinking force. When the compressive force is extremely large, misalignment occurs to the active region and the crystal of the insulating film, causing point defects and cracks on elements. The point defects and cracks serve as the recombination center in energy gaps and thus increase leakage current, causing defective elements. Even when the stress is several tens to several hundreds of megapascals, which is a degree short of causing defects or cracks, a transistor formed in the active region will be distorted. In particular, when forming in the active region a metal-insulator-semiconductor field effect transistor (MISFET), which is minute in size, then effects by the stress are extensive even to the channel region, which will be distorted.
Distortion is influential to the electrical characteristics of the MISFET in two viewpoints. For one, the energy band structure of silicon is deformed, and for the other, the diffusion coefficient of impurities is varied.
Since the energy band originates in crystal periodicity (periodic potential), crystal distortion directly affects the structure of the energy band. There are roughly two effects on the energy band structure, one being that a band which was degenerated in accordance with the symmetry of the crystal lattice is split by distortion. This increases carriers that contribute to electrical conduction in the band of lower energy. The larger the effective mass of the carriers of the lower energy band becomes, the less carrier mobility becomes, and vice versa. Because carrier mobility is approximately proportionate to drain current, the drain current is also varied by the distortion. When there is an energy splitting far exceeding thermal fluctuation (up to 40 meV), the probability of inter-valley scattering (optical phonon scattering) decreases, thereby increasing carrier mobility. Additionally, because the band ends are displaced in varied ways, leakage current at the junction, junction capacitance, and the threshold voltage of the MISFET are also influenced.
As the other effect that distortion has on the energy band structure, the curvature of energy relative to wavenumber is varied. The curvature of energy is inversely proportionate to the effective mass of carriers, that is, proportionate to carrier mobility, and thus the electrical characteristics of the MISFET are directly affected by variations in curvature. Although variations in curvature also affect the probability of inner-valley scattering (acoustic phonon scattering), this is considered to be of little consequence in the practically applicable range.
Variations in the diffusion coefficient of impurities due to distortion causes, for example, a reduced diffusion coefficient of boron in compressive stress, which in turn causes variations in the threshold voltage in an N-channel MISFET (NMISFET) using boron for channel implantation or pocket implantation.
Among the aforementioned various effects that distortion has on the electrical and physical characteristics of the MISFET, variations in carrier mobility and in threshold voltage are particularly critical in that integrated circuits are largely affected.
In MISFETs of sub-90 nm for the minimal line width, in view of recent difficulty in improving the driving force by the conventional scaling, an attempt is being made to develop technology that utilizes the improvement in carrier mobility due to distortion. Stress (STI stress) generated by STI depends on the layout pattern of the active region and the STI region, the degree of distortion applied to the transistor being varied upon change in the layout pattern. Thus, in a standard cell and custom design of the cell based system, which involves complicated layout patterns, there are transistors of various characteristics depending on the layout pattern, even though these transistors have the same gate length and gate width. Variations in the characteristics of transistors depending on the layout pattern are a cause of calculation errors in circuit simulation. In order to improve the accuracy of prediction of circuit simulation, the dependency of STI stress on the layout pattern must be taken into consideration in the circuit simulation. For example, patent document 1, the entire contents of which being herein incorporated by reference, describes a simulation that takes into consideration the dependency of STI stress on the layout pattern.
A simulation described in patent document 1 will be described below referring to a drawing. FIG. 13 is a schematic diagram of a layout pattern of a MISFET where an STI region formed of an insulating film and electrically isolating an element and an active region surrounded by the STI region are formed. Above the active region, a gate electrode is formed with an insulating film in between, and thus a MISFET is complete for operation.
Stress occurs at the interface between the active region and the STI region, and compressible stress occurs at the channel portion of the MISFET. Although pulling stress may occur depending on a method by which the element isolating film in the STI region is formed, the resulting model will not be essentially different; only with some changes occur in sign and size of model parameters in the simulation. Although the size of stress occasionally reaches 500 MPa, the lattice distortion of silicon is small relative to the lattice constant, at most approximately 1%. Therefore, the stress and distortion are in a linear relationship, that is, can be represented by Hooke's law. In the case of a distortion with a stress of equal to or lower than 500 MPa, the distortion and carrier mobility are in a linear relationship, that is, a piezoresistance model can be well applied here. Therefore, the stress is proportionate to carrier mobility.
Japanese Patent Application Publication No. 2003-264242, the entire contents of which being herein incorporated by reference, proposes a model in which carrier mobility is inversely proportionate to an active area width SA, which is the distance between a gate end and an active area end in the length direction of the gate, which is realized by assuming that stress is inversely proportionate to the active area width SA. The publication also proposes a model for the threshold voltage of a MISFET on the analogy of the model for carrier mobility, i.e., the threshold voltage is inversely proportionate to the active area width SA. Other examples include a BSIM4 model, developed by the University of California, Berkley. The BSIM4 model is in use incorporating a model in which carrier mobility and threshold voltage are inversely proportionate to (SA+0.5×L). These conventional models can accurately represent variations in transistor characteristics due to stress in MISFETs of simple layout patterns such as the one shown in FIG. 13.
Actually, however, a plurality of transistors are formed, and it is known that the size of STI stress applied to the active region depends not only on the active area width SA but on, for example, the area ratio of the adjacent active region (see, for example, Victor Moroz, et al., “Stress-Aware Design Methodology,” International Symposium on Quality Electronic Design, 2006, pp. 807-812, the entire contents of which being herein incorporated by reference). Thus, the foregoing conventional models increase simulation errors, posing problems including an increased chip area and degraded circuit performance.